SiyaCon Technologies brings 20+ years of cutting-edge expertise in full-chip analog/RF layout, RDL design, bump planning, and DRC/LVS clean-up across advanced nodes from 180nm down to N3/N5. Our team has successfully taped out multiple designs on TSMC (N3/N5/N7/12nm/16nm), Samsung (N4/N6/N8), Intel (3nm/10nm/14nm), and GlobalFoundries (14nm/22nm), delivering low-power, high-performance layouts for mission-critical applications.
We combine hands-on proficiency in Cadence Innovus/Tempus, Synopsys ICC2/StarRC, Siemens Calibre, and Ansys Redhawk SC with custom CAD flow development (Skill/Tcl/Perl) to automate and optimize networking, analog, and mixed-signal designs. From EM/IR analysis to final signoff, we ensure first-time-right silicon with zero compromises on yield, power, or area.
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Expertise
- We combine hands-on proficiency in Cadence Virtuoso, Synopsys Custom Compiler, Siemens Calibre, custom CAD flow development (Skill/Tcl/Perl) to automate and optimize networking, analog, and mixed-signal designs. From EM/IR analysis to final signoff, we ensure first-time-right silicon with zero compromises on yield, power, or area.
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Technology Node
- TSMC : N3 N5 N7 12n 16n 28n 40n 65n
- SAMSUNG : N4 N6 N8
- INTEL : 3n 10n 14n 22n 45n 180n
- GF : 14n 22n
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Function
- Placement,Floorplan and Routing
- Crafted for range of designs from High Performance to Low Power
- Extensive Checklist for Chip Sign-off
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Tools and Languages
- Cadence Virtuoso
- Synopsys Custom Compiler
- Siemens Calibre